/*
 * SPDX-License-Identifier: BSD-3-Clause
 * Copyright(c) 2024 Napatech A/S
 */

/*
 * nthw_fpga_reg_defs_pdb.h
 *
 * Auto-generated file - do *NOT* edit
 *
 */

#ifndef _NTHW_FPGA_REG_DEFS_PDB_
#define _NTHW_FPGA_REG_DEFS_PDB_

/* PDB */
#define NTHW_MOD_PDB (0xa7771bffUL)
#define PDB_CONFIG (0xf73771edUL)
#define PDB_CONFIG_PORT_OFS (0xb5b30335UL)
#define PDB_CONFIG_TS_FORMAT (0x7013d8aUL)
#define PDB_RCP_CTRL (0x28ac2b3aUL)
#define PDB_RCP_CTRL_ADR (0x9d08b0e4UL)
#define PDB_RCP_CTRL_CNT (0x8d002935UL)
#define PDB_RCP_DATA (0x877da923UL)
#define PDB_RCP_DATA_ALIGN (0xe802afb8UL)
#define PDB_RCP_DATA_CRC_OVERWRITE (0x4847dc0aUL)
#define PDB_RCP_DATA_DESCRIPTOR (0x46cb76faUL)
#define PDB_RCP_DATA_DESC_LEN (0xf467e85bUL)
#define PDB_RCP_DATA_DUPLICATE_BIT (0xaeb59507UL)
#define PDB_RCP_DATA_DUPLICATE_EN (0xbab03efeUL)
#define PDB_RCP_DATA_IP_PROT_TNL (0xec892325UL)
#define PDB_RCP_DATA_OFS0_DYN (0xcef3786aUL)
#define PDB_RCP_DATA_OFS0_REL (0xde219bd9UL)
#define PDB_RCP_DATA_OFS1_DYN (0xf39351daUL)
#define PDB_RCP_DATA_OFS1_REL (0xe341b269UL)
#define PDB_RCP_DATA_OFS2_DYN (0xb4332b0aUL)
#define PDB_RCP_DATA_OFS2_REL (0xa4e1c8b9UL)
#define PDB_RCP_DATA_PCAP_KEEP_FCS (0x90bc735eUL)
#define PDB_RCP_DATA_PPC_HSH (0xac10e9f8UL)
#define PDB_RCP_DATA_TX_IGNORE (0x14c556dcUL)
#define PDB_RCP_DATA_TX_NOW (0x479cb22cUL)
#define PDB_RCP_DATA_TX_PORT (0x412a5ed8UL)

#endif	/* _NTHW_FPGA_REG_DEFS_PDB_ */

/*
 * Auto-generated file - do *NOT* edit
 */
