# atmega_rfa1.h

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    00001 /* THIS FILE IS GENERATED by ds2reg.py FROM INPUT Templates/atmega_rfa1.txt */
    00002
    00003 /* Copyright (c) 2009 Axel Wachtler
    00004    All rights reserved.
    00005
    00006    Redistribution and use in source and binary forms, with or without
    00007    modification, are permitted provided that the following conditions
    00008    are met:
    00009
    00010    * Redistributions of source code must retain the above copyright
    00011      notice, this list of conditions and the following disclaimer.
    00012    * Redistributions in binary form must reproduce the above copyright
    00013      notice, this list of conditions and the following disclaimer in the
    00014      documentation and/or other materials provided with the distribution.
    00015    * Neither the name of the authors nor the names of its contributors
    00016      may be used to endorse or promote products derived from this software
    00017      without specific prior written permission.
    00018
    00019    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
    00020    AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
    00021    IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
    00022    ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
    00023    LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
    00024    CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
    00025    SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
    00026    INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
    00027    CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
    00028    ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
    00029    POSSIBILITY OF SUCH DAMAGE. */
    00030
    00031 /* $Id$ */
    00036 #ifndef ATMEGA_128RFA1_H
    00037 #define ATMEGA_128RFA1_H (1)
    00038
    00039 /* === Includes ============================================================== */
    00040 #include <stdint.h>
    00041 /* === Externals ============================================================= */
    00042
    00043 /* === Types ================================================================= */
    00044
    00045 typedef uint8_t trx_ramaddr_t;
    00046 typedef uint8_t trx_regval_t;
    00047 typedef uint8_t trx_regaddr_t;
    00048
    00049 /* === Macros ================================================================ */
    00051 #define RG_TRX_STATUS (0x1)
    00052
    00053   #define SR_CCA_DONE 0x1,0x80,7
    00054
    00055   #define SR_CCA_STATUS 0x1,0x40,6
    00056
    00057   #define SR_TRX_STATUS 0x1,0x1f,0
    00058
    00059 #define RG_TRX_STATE (0x2)
    00060
    00061   #define SR_TRAC_STATUS 0x2,0xe0,5
    00062
    00063   #define SR_TRX_CMD 0x2,0x1f,0
    00064
    00065 #define RG_TRX_CTRL_0 (0x3)
    00066
    00067   #define SR_PAD_IO 0x3,0xe0,5
    00068
    00069   #define SR_PAD_IO_CLKM 0x3,0x10,4
    00070     #define CLKM_2mA (0)
    00071     #define CLKM_4mA (1)
    00072     #define CLKM_6mA (2)
    00073     #define CLKM_8mA (3)
    00074
    00075   #define SR_CLKM_SHA_SEL 0x3,0x8,3
    00076
    00077   #define SR_CLKM_CTRL 0x3,0x7,0
    00078     #define CLKM_no_clock (0)
    00079     #define CLKM_1MHz (1)
    00080     #define CLKM_2MHz (2)
    00081     #define CLKM_4MHz (3)
    00082     #define CLKM_8MHz (4)
    00083     #define CLKM_16MHz (5)
    00084
    00085 #define RG_TRX_CTRL_1 (0x4)
    00086
    00087   #define SR_PA_EXT_EN 0x4,0x80,7
    00088
    00089   #define SR_IRQ_2_EXT_EN 0x4,0x40,6
    00090
    00091   #define SR_TX_AUTO_CRC_ON 0x4,0x20,5
    00092
    00093   #define SR_RX_BL_CTRL 0x4,0x10,4
    00094
    00095   #define SR_SPI_CMD_MODE 0x4,0xc,2
    00096
    00097   #define SR_IRQ_POLARITY 0x4,0x1,0
    00098
    00099   #define SR_IRQ_MASK_MODE 0x4,0x2,1
    00100
    00101 #define RG_PHY_TX_PWR (0x5)
    00102
    00103   #define SR_PA_BUF_LT 0x5,0xc0,6
    00104
    00105   #define SR_PA_LT 0x5,0x30,4
    00106
    00107   #define SR_TX_PWR 0x5,0xf,0
    00108
    00109 #define RG_PHY_RSSI (0x6)
    00110
    00111   #define SR_RX_CRC_VALID 0x6,0x80,7
    00112
    00113   #define SR_RND_VALUE 0x6,0x60,5
    00114
    00115   #define SR_RSSI 0x6,0x1f,0
    00116
    00117 #define RG_PHY_ED_LEVEL (0x7)
    00118
    00119   #define SR_ED_LEVEL 0x7,0xff,0
    00120
    00121 #define RG_PHY_CC_CCA (0x8)
    00122
    00123   #define SR_CCA_REQUEST 0x8,0x80,7
    00124
    00125   #define SR_CCA_MODE 0x8,0x60,5
    00126
    00127   #define SR_CHANNEL 0x8,0x1f,0
    00128
    00129 #define RG_CCA_THRES (0x9)
    00130
    00131   #define SR_CCA_ED_THRES 0x9,0xf,0
    00132
    00133 #define RG_RX_CTRL (0xa)
    00134
    00135   #define SR_PDT_THRES 0xa,0xf,0
    00136
    00137 #define RG_SFD_VALUE (0xb)
    00138
    00139   #define SR_SFD_VALUE 0xb,0xff,0
    00140
    00141 #define RG_TRX_CTRL_2 (0xc)
    00142
    00143   #define SR_RX_SAFE_MODE 0xc,0x80,7
    00144
    00145   #define SR_OQPSK_DATA_RATE 0xc,0x3,0
    00146
    00147 #define RG_ANT_DIV (0xd)
    00148
    00149   #define SR_ANT_SEL 0xd,0x80,7
    00150
    00151   #define SR_ANT_DIV_EN 0xd,0x8,3
    00152
    00153   #define SR_ANT_EXT_SW_EN 0xd,0x4,2
    00154
    00155   #define SR_ANT_CTRL 0xd,0x3,0
    00156
    00157 #define RG_IRQ_MASK (0xe)
    00158
    00159   #define SR_MASK_BAT_LOW 0xe,0x80,7
    00160
    00161   #define SR_MASK_TRX_UR 0xe,0x40,6
    00162
    00163   #define SR_MASK_AMI 0xe,0x20,5
    00164
    00165   #define SR_MASK_CCA_ED_READY 0xe,0x10,4
    00166
    00167   #define SR_MASK_TRX_END 0xe,0x8,3
    00168
    00169   #define SR_MASK_TRX_START 0xe,0x4,2
    00170
    00171   #define SR_MASK_PLL_LOCK 0xe,0x1,0
    00172
    00173   #define SR_MASK_PLL_UNLOCK 0xe,0x2,1
    00174
    00175 #define RG_IRQ_STATUS (0xf)
    00176
    00177   #define SR_BAT_LOW 0xf,0x80,7
    00178
    00179   #define SR_TRX_UR 0xf,0x40,6
    00180
    00181   #define SR_AMI 0xf,0x20,5
    00182
    00183   #define SR_CCA_ED_READY 0xf,0x10,4
    00184
    00185   #define SR_RX_END 0xf,0x8,3
    00186
    00187   #define SR_RX_START 0xf,0x4,2
    00188
    00189   #define SR_PLL_LOCK 0xf,0x1,0
    00190
    00191   #define SR_PLL_UNLOCK 0xf,0x2,1
    00192
    00193 #define RG_VREG_CTRL (0x10)
    00194
    00195   #define SR_AVREG_EXT 0x10,0x80,7
    00196
    00197   #define SR_AVDD_OK 0x10,0x40,6
    00198
    00199   #define SR_DVREG_EXT 0x10,0x8,3
    00200
    00201   #define SR_DVDD_OK 0x10,0x4,2
    00202
    00203 #define RG_BATMON (0x11)
    00204
    00205   #define SR_BATMON_OK 0x11,0x20,5
    00206
    00207   #define SR_BATMON_HR 0x11,0x10,4
    00208
    00209   #define SR_BATMON_VTH 0x11,0xf,0
    00210
    00211 #define RG_XOSC_CTRL (0x12)
    00212
    00213   #define SR_XTAL_MODE 0x12,0xf0,4
    00214
    00215   #define SR_XTAL_TRIM 0x12,0xf,0
    00216
    00217 #define RG_RX_SYN (0x15)
    00218
    00219   #define SR_RX_PDT_DIS 0x15,0x80,7
    00220
    00221   #define SR_RX_PDT_LEVEL 0x15,0xf,0
    00222
    00223 #define RG_XAH_CTRL_1 (0x17)
    00224
    00225   #define SR_AACK_FLTR_RES_FT 0x17,0x20,5
    00226
    00227   #define SR_AACK_UPLD_RES_FT 0x17,0x10,4
    00228
    00229   #define SR_AACK_ACK_TIME 0x17,0x4,2
    00230
    00231   #define SR_AACK_PROM_MODE 0x17,0x2,1
    00232
    00233 #define RG_FTN_CTRL (0x18)
    00234
    00235   #define SR_FTN_START 0x18,0x80,7
    00236
    00237 #define RG_PLL_CF (0x1a)
    00238
    00239   #define SR_PLL_CF_START 0x1a,0x80,7
    00240
    00241 #define RG_PLL_DCU (0x1b)
    00242
    00243   #define SR_PLL_DCU_START 0x1b,0x80,7
    00244
    00245 #define RG_PART_NUM (0x1c)
    00246
    00247   #define SR_PART_NUM 0x1c,0xff,0
    00248     #define RFA1_PART_NUM (131)
    00249
    00250 #define RG_VERSION_NUM (0x1d)
    00251
    00252   #define SR_VERSION_NUM 0x1d,0xff,0
    00253     #define RFA1_VERSION_NUM_NONE (0)
    00254     #define RFA1_VERSION_NUM_A (2)
    00255     #define RFA1_VERSION_NUM_B (2)
    00256     #define RFA1_VERSION_NUM_C (3)
    00257     #define RFA1_VERSION_NUM_D (4)
    00258
    00259 #define RG_MAN_ID_0 (0x1e)
    00260
    00261   #define SR_MAN_ID_0 0x1e,0xff,0
    00262
    00263 #define RG_MAN_ID_1 (0x1f)
    00264
    00265   #define SR_MAN_ID_1 0x1f,0xff,0
    00266
    00267 #define RG_SHORT_ADDR_0 (0x20)
    00268
    00269   #define SR_SHORT_ADDR_0 0x20,0xff,0
    00270
    00271 #define RG_SHORT_ADDR_1 (0x21)
    00272
    00273   #define SR_SHORT_ADDR_1 0x21,0xff,0
    00274
    00275 #define RG_PAN_ID_0 (0x22)
    00276
    00277   #define SR_PAN_ID_0 0x22,0xff,0
    00278
    00279 #define RG_PAN_ID_1 (0x23)
    00280
    00281   #define SR_PAN_ID_1 0x23,0xff,0
    00282
    00283 #define RG_IEEE_ADDR_0 (0x24)
    00284
    00285   #define SR_IEEE_ADDR_0 0x24,0xff,0
    00286
    00287 #define RG_IEEE_ADDR_1 (0x25)
    00288
    00289   #define SR_IEEE_ADDR_1 0x25,0xff,0
    00290
    00291 #define RG_IEEE_ADDR_2 (0x26)
    00292
    00293   #define SR_IEEE_ADDR_2 0x26,0xff,0
    00294
    00295 #define RG_IEEE_ADDR_3 (0x27)
    00296
    00297   #define SR_IEEE_ADDR_3 0x27,0xff,0
    00298
    00299 #define RG_IEEE_ADDR_4 (0x28)
    00300
    00301   #define SR_IEEE_ADDR_4 0x28,0xff,0
    00302
    00303 #define RG_IEEE_ADDR_5 (0x29)
    00304
    00305   #define SR_IEEE_ADDR_5 0x29,0xff,0
    00306
    00307 #define RG_IEEE_ADDR_6 (0x2a)
    00308
    00309   #define SR_IEEE_ADDR_6 0x2a,0xff,0
    00310
    00311 #define RG_IEEE_ADDR_7 (0x2b)
    00312
    00313   #define SR_IEEE_ADDR_7 0x2b,0xff,0
    00314
    00315 #define RG_XAH_CTRL_0 (0x2c)
    00316
    00317   #define SR_MAX_FRAME_RETRES 0x2c,0xf0,4
    00318
    00319   #define SR_SLOTTED_OPERATION 0x2c,0x1,0
    00320
    00321   #define SR_MAX_CSMA_RETRES 0x2c,0xe,1
    00322
    00323 #define RG_CSMA_SEED_0 (0x2d)
    00324
    00325   #define SR_CSMA_SEED_0 0x2d,0xff,0
    00326
    00327 #define RG_CSMA_SEED_1 (0x2e)
    00328
    00329   #define SR_AACK_FVN_MODE 0x2e,0xc0,6
    00330
    00331   #define SR_AACK_SET_PD 0x2e,0x20,5
    00332
    00333   #define SR_AACK_DIS_ACK 0x2e,0x10,4
    00334
    00335   #define SR_AACK_I_AM_COORD 0x2e,0x8,3
    00336
    00337   #define SR_CSMA_SEED_1 0x2e,0x7,0
    00338
    00339 #define RG_CSMA_BE (0x2f)
    00340
    00341   #define SR_MAX_BE 0x2f,0xf0,4
    00342
    00343   #define SR_MIN_BE 0x2f,0xf,0
    00344
    00345 #define RADIO_NAME "ATmega128RFA1"
    00346
    00347 #define RADIO_PART_NUM (RFA1_PART_NUM)
    00348
    00349 #if RADIO_TYPE == RADIO_ATMEGA128RFA1_A
    00350 # define RADIO_VERSION_NUM (RFA1_VERSION_NUM_A)
    00351 #elif RADIO_TYPE == RADIO_ATMEGA128RFA1_B
    00352 # define RADIO_VERSION_NUM (RFA1_VERSION_NUM_B)
    00353 #elif RADIO_TYPE == RADIO_ATMEGA128RFA1_C
    00354 # define RADIO_VERSION_NUM (RFA1_VERSION_NUM_C)
    00355 #elif RADIO_TYPE == RADIO_ATMEGA128RFA1_D
    00356 # define RADIO_VERSION_NUM (RFA1_VERSION_NUM_D)
    00357 #endif
    00358
    00359
    00361 #define TRX_REGISTER_BASEADDR (0x140)
    00362
    00363 #define AES_REGISTER_BASEADDR (0x13c)
    00364
    00365
    00366 #define TRX_IF_RFA1    (1)     /* interfaces to RFA1 rather than SPI */
    00367
    00368 #define TRX_CMD_RADDR_MASK   (0x3f)
    00369
    00371 #define TRX_RESET_TIME_US    (6)
    00372
    00374 #define TRX_INIT_TIME_US     (510)
    00375
    00377 #define TRX_PLL_LOCK_TIME_US     (180)
    00378
    00379
    00381 #define TRX_CCA_TIME_US     (140)
    00382
    00384 #define TRX_IRQ_PLL_LOCK   _BV(0)
    00385
    00387 #define TRX_IRQ_PLL_UNLOCK _BV(1)
    00388
    00390 #define TRX_IRQ_RX_START   _BV(2)
    00391
    00393 #define TRX_IRQ_RX_END     _BV(3)
    00394
    00396 #define TRX_IRQ_CCA_ED     _BV(4)
    00397
    00399 #define TRX_IRQ_AMI        _BV(5)
    00400
    00402 #define TRX_IRQ_TX_END     _BV(6)
    00403
    00405 #define TRX_MIN_CHANNEL (11)
    00406
    00408 #define TRX_MAX_CHANNEL (26)
    00409
    00411 #define TRX_NB_CHANNELS (16)
    00412
    00417 #define TRX_SUPPORTED_CHANNELS  (0x7fff800UL)
    00418
    00419 #define TRX_SUPPORTS_BAND_2400 (1)
    00420
    00424 #define TRX_SUPPORTED_PAGES     (42)
    00425
    00427 #define TRX_OQPSK250  (0)
    00428
    00430 #define TRX_OQPSK500  (1)
    00431
    00433 #define TRX_OQPSK1000 (2)
    00434
    00435 #define TRX_OQPSK2000 (3)
    00436
    00437 #define TRX_NONE      (255)
    00438
    00439 #ifdef __cplusplus
    00440 extern "C" {
    00441 #endif
    00442
    00443 extern volatile uint8_t SHADOW_IRQ_MASK;
    00444 static inline void disable_all_trx_irqs(void)
    00445 {
    00446     SHADOW_IRQ_MASK = IRQ_MASK;
    00447     IRQ_MASK = 0;
    00448 }
    00449
    00450 static inline void enable_all_trx_irqs(void)
    00451 {
    00452     IRQ_MASK= SHADOW_IRQ_MASK;
    00453 }
    00454
    00455 #ifdef __cplusplus
    00456 } /* extern "C" */
    00457 #endif
    00458
    00459 #endif /* ifndef ATMEGA_128RFA1_H */